Interrupts Introduction

1. Interrupts in the 8085 Microprocessor

1.1 Definition

An interrupt is a signal that temporarily halts the normal execution of a program so that the CPU can service a high-priority event or request. Once the interrupt has been serviced, the CPU resumes the previously executing program. The 8085 microprocessor features 5 hardware interrupt lines and supports both hardware and software interrupts.

1.2 Types of Interrupts in 8085

• A. Hardware Interrupts

  Triggered externally via pins on the processor. Classified as:

  • Maskable Interrupts: Can be enabled/disabled (masked/unmasked).
  • Non-Maskable Interrupts: Cannot be disabled.

  Interrupt	Maskable	Trigger Type	Vector Address	Priority	Typical Use-Case	Notes
  TRAP	No	Edge + Level	0024H	Highest	Power failure, emergency	Non-maskable, both edge and level sensitive
  RST 7.5	Yes	Rising Edge	003CH	High	Fast sensors	Maskable via SIM, edge-triggered
  RST 6.5	Yes	High Level	0034H	Medium	Keyboard input	Maskable via SIM, level-triggered
  RST 5.5	Yes	High Level	002CH	Low	Printer, slow devices	Maskable via SIM, level-triggered
  INTR	Yes	High Level	Non-vectored	Lowest	General peripherals	Requires external hardware for vector

  • TRAP (Non-Maskable, Highest Priority)

    • Trigger: Simultaneous rising edge and high level on TRAP pin.
    • Vector Address: 0024H.
    • Example: Emergency shutdown, power failure signal.
    • Notes: TRAP cannot be disabled, making it suitable for critical events.

  • RST 7.5 (Maskable, Edge-Triggered)

    • Trigger: Rising edge on RST 7.5 pin.
    • Vector Address: 003CH.
    • Masking: Can be enabled/disabled with SIM instruction.
    • Example: High-speed data acquisition from sensors.

  • RST 6.5 & RST 5.5 (Maskable, Level-Triggered)

    • Trigger: High level on RST 6.5 (0034H) or RST 5.5 (002CH).
    • Example: RST 6.5 for moderate-speed devices (keyboards); RST 5.5 for low-priority devices (printers).
    • Masking: Enabled/disabled with SIM.

  • INTR (Maskable, Lowest Priority, Non-Vectored)

    • Trigger: High level on INTR pin.
    • Not vectored: Requires the external device to supply RST opcode during INTA cycle.
    • Example: General purpose peripherals, slow devices.

• B. Software Interrupts

  • Initiated by executing specific instructions (RST n).
  • Vectored Interrupts: Each RST n instruction jumps to a fixed address.

  Instruction	Address
  RST 0	0000H
  RST 1	0008H
  RST 2	0010H
  …	…
  RST 7	0038H

  • Use Cases: Debugging, system calls, invoking operating system routines, user-defined interrupts.

1.3 Key Concepts

• Priority Order

  TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR.

• Masking and Enabling/Disabling

  • SIM (Set Interrupt Mask) instruction: Masks/unmasks individual interrupts.
  • RIM (Read Interrupt Mask) instruction: Reads current interrupt mask settings.
  • EI (Enable Interrupts): Enables all maskable interrupts.
  • DI (Disable Interrupts): Disables all maskable interrupts.

• Vectored vs. Non-Vectored Interrupts

  • Vectored: Processor jumps directly to a predefined ISR address (TRAP, RST 5.5/6.5/7.5).
  • Non-Vectored: ISR address is supplied externally during INTA (INTR).

• Interrupt Service Routine (ISR)

  • When an interrupt occurs, the processor pushes the address of the next instruction to the stack and jumps to the ISR.
  • After execution, a RET (return) instruction brings the processor back to the main program.

1.4 Interrupt Timing & Handling Sequence

1. Interrupt Request detected.
2. Current instruction completes (8085 is not truly pre-emptive).
3. Interrupt acknowledge and vectoring.
4. ISR executed; main program resumes after ISR (context is restored).

1.5 Use Cases in 8085

• Power failure handling (TRAP).
• Keyboard debouncing (RST 6.5).
• Periodic polling replaced by INTR for efficiency.

2. Interrupts in Embedded Systems

2.1 Definition

Interrupts are signals that inform a processor or microcontroller about an event, causing the normal program flow to be suspended so the event can be serviced immediately. Used extensively in real-time embedded systems for event-driven operation.

2.2 Types of Interrupts

• A. Hardware Interrupts

  • External Interrupts: Triggered by signals from outside the chip (e.g., GPIO pin, sensor input).
  • Internal Interrupts: Generated by on-chip peripherals (e.g., Timer overflow, ADC complete, UART RX).

  Example Peripheral	Type	Use Case
  GPIO (button)	External	User input, alarms
  Timer/Counter	Internal	Periodic tasks, PWM generation
  ADC Conversion	Internal	Data acquisition from sensors
  UART RX	Internal	Serial data reception

• B. Software Interrupts (Traps/Exceptions)

  • Triggered by program conditions: division by zero, invalid opcode, stack overflow, or explicit SWI instruction.
  • Managed by processor’s exception logic.

• C. Other Classifications

  • Edge-Triggered: Responds to signal transitions (rising/falling edge).

    • Example: Rotary encoder pulse detection.

  • Level-Triggered: Responds to constant logic levels (high or low).

    • Example: Button held down for pause.

  • Non-Maskable Interrupts (NMI): Cannot be disabled, for critical failure detection.

  • Timer Interrupts: Periodic scheduling, RTOS tick, timeouts.

  • Watchdog Timer Interrupts: System reset if main code fails to reset the timer (“kicking the dog”).

2.3 Interrupt Handling Mechanisms

• Interrupt Vector Table (IVT)

  • A table storing the starting addresses of all ISRs.
  • On interrupt, processor jumps to the corresponding address in IVT.
  • Example: ARM Cortex-M stores IVT in flash at 0x00000000.

• Nested Interrupts

  • Allows higher-priority interrupts to pre-empt ongoing ISRs.
  • Managed by NVIC (Nested Vectored Interrupt Controller) in ARM MCUs.

• Context Saving & Restoring

  • Processor automatically (or manually, in simple systems) saves CPU registers, flags, and PC (Program Counter) before entering ISR and restores them after ISR completion.

• Interrupt Latency

  • The delay between interrupt request and start of ISR.
  • Influenced by instruction pipeline, context saving, and interrupt masking.

2.4 Practical Embedded Examples

3. Comparison: 8085 vs. Modern Embedded Systems

Interrupt Priorities

• Determines which interrupt is handled first if multiple occur.
• Example Priority Order (x86):
  1. Non-Maskable Interrupts (NMI)
  2. Hardware Interrupts (IRQ0-IRQ15)
  3. Software Interrupts

Context Switching

Definition

Context switching is the process of saving and restoring the state of a CPU to allow multiple processes to share the CPU. It is critical for multitasking OS.

When Does It Occur?

• Timer interrupt (preemptive multitasking).
• Process voluntarily yields CPU (e.g., system call).
• Higher-priority process preempts a lower-priority one.

Steps in Context Switching

1. Save Current Context:
   • CPU registers, program counter, and stack pointer are saved in the Process Control Block (PCB).
2. Update PCB:
   • Mark the current process as “waiting” or “ready”.
3. Schedule Next Process:
   • OS scheduler selects the next process to run.
4. Restore New Context:
   • Load registers and PC from the new process’s PCB.
5. Resume Execution:
   • Jump to the new process’s last execution point.

Example (Pseudocode):

void context_switch(PCB *old, PCB *new) {
    // Save old process state
    old->registers = CPU_REGISTERS;
    old->pc = CPU_PC;

    // Load new process state
    CPU_REGISTERS = new->registers;
    CPU_PC = new->pc;
}

Overhead and Challenges

• Time-consuming (hundreds to thousands of CPU cycles).
• Can reduce system throughput if too frequent.
• Requires careful design to avoid race conditions.

Example (Timer-Driven Context Switching)

1. Timer interrupt fires every 10ms.
2. OS saves the state of Process A.
3. Scheduler selects Process B (next in queue).
4. OS restores Process B’s state and resumes it.

Relationship Between Interrupts and Context Switching

• Interrupts trigger context switches in preemptive multitasking.
• Example Flow:
  1. Timer interrupt → ISR handler → Scheduler → Context switch to Process B.

4. Summary

• 8085: Simple, fixed-priority interrupt system ideal for learning basics of CPU interrupts and microcontroller principles.
• Embedded Systems: More complex, support advanced real-time handling, multi-level priorities, nesting, and a vast range of peripherals and use-cases.
• Key Concept: Interrupts are crucial for responsive, efficient embedded applications, enabling real-time event management and optimal resource utilization.